VOSYSmonitor, a Low Latency Monitor Layer for Mixed-Criticality Systems on ARMv8-A

With the emergence of multicore embedded System on Chip (SoC), the integration of several applications with different levels of criticality on the same platform is becoming increasingly popular. These platforms, known as mixed-criticality systems, need to meet numerous requirements such as real-time constraints, Operating System (OS) scheduling, memory and OSes isolation. To construct mixed-criticality systems, various solutions, based on virtualization extensions, have been presented where OSes are contained in a Virtual Machine (VM) through the use of a hypervisor. However, such implementations usually lack hardware features to ensure a full isolation of other bus masters (e.g., Direct Memory Access (DMA) peripherals, Graphics Processing Unit (GPU)) between OSes. Furthermore on multicore implementation, one core is usually dedicated to one OS, causing CPU underutilization. To address these issues, this paper presents VOSYSmonitor, a multi-core software layer, which allows the co-execution of a safety-critical Real-Time Operating System (RTOS) and a non-critical General Purpose Operating System (GPOS) on the same hardware ARMv8-A platform. VOSYSmonitor main differentiation factors with the known solutions is the possibility for a processor to switch between secure and non-secure code execution at runtime. The partitioning is ensured by the ARM TrustZone technology, thus allowing to preserve the usage of virtualization features for the GPOS. VOSYSmonitor architecture will be detailed in this paper, while benchmarking its performance versus other known solutions

VOSYSmonitor, a TrustZone-based Hypervisor for ISO 26262 Mixed-critical System

With the emergence of multicore embedded System on Chip (SoC), the integration of several applications with different levels of criticality on the same platform is becoming increasingly popular. These platforms, known as mixed-criticality systems, need to meet numerous requirements (e.g. real-time constraints, multiple Operating Systems (OS) scheduling, pro- viding temporal and spatial isolation). In this context Virtual Open Systems has developed VOSYSmonitor, a thin software layer, which allows the co-execution of a safety-critical and non- critical applications on a single ARM-based multi-core SoC. This software element has been developed according to the ISO 26262 standard. One of the key aspects of this standard is the control of random and systematic failures, including the ones induced by faulty or aging hardware. In the case of a software component, the means to detect anomalies on the hardware are limited and depend on choices of the manufacturer (i.e. implementation of Dual redundant Core Lock step (DCLS)). However, the software is able to check a part of these failures. It can be by either reading the configuration registers of a peripheral, or checking the sanity of a memory region. The purpose of this paper is to showcase how a safety-related software element (e.g. VOSYSmonitor) can detect and recover from failures, while ensuring that the safety-related goals are still reached

Genetic engineering of marine cyanophages reveals integration but not lysogeny in T7-like cyanophages

Marine cyanobacteria of the genera Synechococcus and Prochlorococcus are the most abundant photosynthetic organisms on earth, spanning vast regions of the oceans and contributing significantly to global primary production. Their viruses (cyanophages) greatly influence cyanobacterial ecology and evolution. Although many cyanophage genomes have been sequenced, insight into the functional role of cyanophage genes is limited by the lack of a cyanophage genetic engineering system. Here, we describe a simple, generalizable method for genetic engineering of cyanophages from multiple families, that we named REEP for REcombination, Enrichment and PCR screening. This method enables direct investigation of key cyanophage genes, and its simplicity makes it adaptable to other ecologically relevant host-virus systems. T7-like cyanophages often carry integrase genes and attachment sites, yet exhibit lytic infection dynamics. Here, using REEP, we investigated their ability to integrate and maintain a lysogenic life cycle. We found that these cyanophages integrate into the host genome and that the integrase and attachment site are required for integration. However, stable lysogens did not form. The frequency of integration was found to be low in both lab cultures and the oceans. These findings suggest that T7-like cyanophage integration is transient and is not part of a classical lysogenic cycle

Survey on memory and devices disaggregation solutions for HPC systems

International audience<p>Traditionally, HPC workloads are characterized by different requirements in CPU and memory resources, which in addition vary over time in unpredictable manner. For this reason, HPC system designs, assuming physical co-location of CPU and memory on a single motherboard, strongly limit scalability, while leading to inefficient resources over-provisioning. Also, peripherals available in the system need to be globally accessible to allow optimal usage. In this context, modern HPC designs tend to support disaggregated memory, compute nodes, remote peripherals and hardware extensions to support virtualization techniques. In this paper, a qualitative survey on different attempts of memory and devices disaggregation is conducted. In addition, alternative future directions for devices disaggregation are proposed in the context of the work planned in the H2020 dRedBox project.</p

Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach

Power consumption and high compute density are the key factors to be considered when building a compute node for the upcoming Exascale revolution. Current architectural design and manufacturing technologies are not able to provide the requested level of density and power efficiency to realise an operational Exascale machine. A disruptive change in the hardware design and integration process is needed in order to cope with the requirements of this forthcoming computing target. This paper presents the ExaNoDe H2020 research project aiming to design a highly energy efficient and highly integrated heterogeneous compute node targeting Exascale level computing, mixing low-power processors, heterogeneous co-processors and using advanced hardware integration technologies with the novel UNIMEM Global Address Space memory system

Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach

Power consumption and high compute density are the key factors to be considered when building a compute node for the upcoming Exascale revolution. Current architectural design and manufacturing technologies are not able to provide the requested level of density and power efficiency to realise an operational Exascale machine. A disruptive change in the hardware design and integration process is needed in order to cope with the requirements of this forthcoming computing target. This paper presents the ExaNoDe H2020 research project aiming to design a highly energy efficient and highly integrated heterogeneous compute node targeting Exascale level computing, mixing low-power processors, heterogeneous co-processors and using advanced hardware integration technologies with the novel UNIMEM Global Address Space memory system.This work was supported by the ExaNoDe project that has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No. 671578. The work presented in this paper reflects only authors’ view and the European Commission is not responsible for any use that may be made of the information it contains.Peer Reviewe